1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of gate insulating films different in the film material or film thickness and a method of fabricating the same and, more particularly, to a semiconductor device in which gate insulating films are separately formed and a method of fabricating the same.
2. Description of the Related Art
As an electrically erasable and programmable nonvolatile semiconductor memory (EEPROM), a MONOS EEPROM which stores electric charge into a silicon nitride film is known. MONOS represents Metal-Oxide-Nitride-Oxide-Semiconductor, and typically represents metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor. In this MONOS EEPROM, a gate insulating film of a memory cell is an ONO stacked film, whereas a transistor forming a peripheral circuit has a MOS structure in which a silicon oxide film is a gate insulating film. Therefore, these two components must be separately formed in the fabrication of a MONOS EEPROM.
In a method of separately forming transistors having different gate insulating films, it is important to satisfy three points: the reliability of the gate insulating films, high performance of a memory cell, and a sufficient process margin.
A method described in Jpn. Pat. Appln. KOKAI Publication No. 8-330436 is a method of separately forming transistors having different gate insulating films. In this prior art, after a device isolation region is formed by LOCOS, two gate oxide films different in film thickness and gate electrodes are formed. Recently, trench device isolation is beginning to be used instead of LOCOS. Compared to LOCOS, trench device isolation can realize a high device isolation breakdown voltage with a very small device isolation width.
A method of separately forming a MONOS memory cell and a MOS peripheral transistor by using trench device isolation shown in FIGS. 60A to 60E will be described below. In this method, gate insulating films and gate electrodes are formed after the formation of device isolation regions, as in the technique described in Jpn. Pat. Appln. KOKAI Publication No. 8-330436 as the prior art described above. Referring to FIGS. 60A to 60E, MC indicates a memory cell region, and PTR indicates a peripheral transistor region.
First, as shown in FIG. 60A, device isolation regions 201 are formed in a semiconductor substrate 200. Next, as shown in FIG. 60B, a sacrificial oxide film is removed by wet etching, and a gate insulating film 202 and a gate electrode 203 of a peripheral circuit transistor are formed. In addition, a peripheral circuit region is covered with a resist layer 204.
As shown in FIG. 60C, the gate electrode and the gate oxide film in a memory cell region are removed. After an ONO film 205 as a gate insulating film of a memory cell is deposited on the entire surface of the semiconductor substrate 200, a memory cell gate electrode 206 is deposited. Subsequently, the memory cell region is covered with a resist layer 207, and the memory cell gate electrode 206 and the ONO film 205 in the peripheral circuit region are removed. Finally, as shown in FIG. 60D, the resist layer 207 is removed. As a consequence, the peripheral MOS transistor and the MONOS memory cell can be separately formed.
Unfortunately, this method has the following problems. The first problem is related to the nonuniformity of the ONO film. That is, since the edges of the device isolation regions are not flat but have steps, it is difficult to deposit the ONO film with a uniform film thickness and uniform film quality. This causes variations in the program characteristic and data holding characteristic of the memory cell.
The second problem is related to a parasitic transistor as shown in FIG. 60E which is an enlarged view of a region TP in FIG. 60D. During wet etching before the formation of the gate insulating film, a buried oxide film in a device isolation trench is partially etched on the edge of the device isolation region. The gate electrode enters this etched portion to form a parasitic transistor. This causes characteristic variations in both the memory cell and the peripheral transistor.
In this prior art, the peripheral transistor is formed first and then the memory cell transistor is formed. However, the above problems are not solved even if the formation order is changed; the problems arise because the gate insulating films are separately formed after the formation of the device isolation regions. A prior art to be explained below solves the above problems by separately forming gate insulating films before device isolation regions are formed.
As a method of solving the above problems, “1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 102–103, “A Self-Aligned STI Process Integration for Low Cost and Highly Reliable 1 Gbit Flash Memories”, Y. Takeuchi et al.” describes a self-aligned trench device isolation method which forms trench device isolation regions after gate insulating films and gate electrodes are formed. The steps of this fabrication method of separately forming a MONOS cell and a MOS peripheral transistor will be described with reference to FIGS. 61A to 61D.
First, as shown in FIG. 61A, impurity implantation for wells and channels is performed to form a memory cell well 205 and a peripheral circuit well 206. Next, an ONO film 207 and a silicon oxide film 208 are separately formed. A polysilicon gate electrode 209 and a silicon nitride film 210 as a mask are deposited. As shown in FIG. 61B, device isolation trenches 211 are formed in a semiconductor substrate 200. A silicon oxide film 212 is deposited on the exposed surface to fill the device isolation trenches 211.
As shown in FIG. 61C, the silicon oxide film 212 is removed by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 210 as a mask is exposed, thereby planarizing the surface. Subsequently, as shown in FIG. 61D, the silicon nitride film 210 as a mask is removed, and a tungsten silicide layer 213 is deposited. A memory cell isolation region 214, a boundary area device isolation region 215, and a peripheral circuit device isolation region 216 are formed, and the individual gate electrodes are processed. This method solves the problems such as the nonuniformity of the ONO film and the etching of the device isolation oxide film as shown in FIG. 60E.